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Volumn 1, Issue , 1998, Pages 196-199

Modified approach to automata state encoding for LUT FPGA implementation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; ENCODING (SYMBOLS); FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MERGING; STATE ASSIGNMENT;

EID: 0141873665     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1998.711798     Document Type: Conference Paper
Times cited : (3)

References (11)
  • 1
    • 84888989466 scopus 로고
    • A Unified Approach for FSM Synthesis on FPGA Architecture
    • Liverpool, UK, Sept
    • Burgun, L., Dictus, N., Prado Lopes, E., Sazwary, C., A Unified Approach for FSM Synthesis on FPGA Architecture - EUROMICR0'94, Liverpool, UK, Sept., 1994, pp. 660-668
    • (1994) EUROMICR0'94 , pp. 660-668
    • Burgun, L.1    Dictus, N.2    Prado Lopes, E.3    Sazwary, C.4
  • 2
    • 84940567069 scopus 로고    scopus 로고
    • Support-Based State Encoding Targeting FSM Optimal LUT FPGA Implementation
    • Grenoble, France
    • Grass, W., Lemberski, I., Support-Based State Encoding Targeting FSM Optimal LUT FPGA Implementation. - IWLAS'97, Grenoble, France, 1997, pp. 97-104.
    • (1997) IWLAS'97 , pp. 97-104
    • Grass, W.1    Lemberski, I.2
  • 4
    • 0030652322 scopus 로고    scopus 로고
    • Information Relationships and Measures: An Analysis Apparatus for Efficient Information System Synthesis
    • Budapest, Hungary, Sept. 1-4
    • Jozwiak, L., Information Relationships and Measures: An Analysis Apparatus for Efficient Information System Synthesis. - EUROMICR0'97, Budapest, Hungary, Sept. 1-4, 1997, pp. 13-23.
    • (1997) EUROMICR0'97 , pp. 13-23
    • Jozwiak, L.1
  • 5
    • 0005350416 scopus 로고    scopus 로고
    • Input Support minimization for Efficient PLD and FPGA Synthesis
    • Grenoble, France, Dec.16-18
    • Jozwiak, L., Konieczny, P.: Input Support minimization for Efficient PLD and FPGA Synthesis. - IWLAS'96, Grenoble, France, Dec.16-18, 1996, pp. 30-37.
    • (1996) IWLAS'96 , pp. 30-37
    • Jozwiak, L.1    Konieczny, P.2
  • 6
    • 0004529209 scopus 로고
    • Synthesis of Multi-Level Logic from Symbolic High-Level Description Languages
    • August
    • Lin, B., Newton, A.: Synthesis of Multi-Level Logic from Symbolic High-Level Description Languages. - Proc. Int. Conf. on VLSI, August, 1989, pp 187-196.
    • (1989) Proc. Int. Conf. on VLSI , pp. 187-196
    • Lin, B.1    Newton, A.2
  • 9
    • 0003934798 scopus 로고    scopus 로고
    • SIS: A System for Sequential Circuit Synthesis
    • Memorandum No. UCB/ERL M 92/41
    • Sentovicli, E.M., et al.: SIS: A System for Sequential Circuit Synthesis. - Electronic Research Laboratory. Memorandum No. UCB/ERL M 92/41, 45 pp.
    • Electronic Research Laboratory
    • Sentovicli, E.M.1
  • 10
    • 0025489532 scopus 로고
    • NOVA - State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation
    • Sept
    • Villa, T., Sangiovanni-Vincentelli, A.: NOVA - State Assignment of Finite State Machines for Optimal Two-Level Logic Implementation - IEEE Trans. CAD, vol. 9, No. 9, Sept., 1990, pp. 905-924.
    • (1990) IEEE Trans. CAD , vol.9 , Issue.9 , pp. 905-924
    • Villa, T.1    Sangiovanni-Vincentelli, A.2
  • 11
    • 0025794585 scopus 로고
    • Optimum and Suboptimum Algorithms for Input Encoding and Its Relationship to Logic Minimization
    • Jan
    • Yang, S., Ciesielski, M.J. - Optimum and Suboptimum Algorithms for Input Encoding and Its Relationship to Logic Minimization-IEEE Trans. CAD, vol. 10, No. 1, Jan., 1991, pp.4-12.
    • (1991) IEEE Trans. CAD , vol.10 , Issue.1 , pp. 4-12
    • Yang, S.1    Ciesielski, M.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.