Process improvements by applying 193 nm lithography to 90 nm logic implant layers

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5038 II, Issue , 2003, Pages 1095-1106

  Yang, D C Owe ^a   Chen, Harrison ^a   Deng, R M ^a   Ho, B C ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

193 nm lithography; CD variation; Implant layers; OPC; OPE; Overlay

Indexed keywords

ION BOMBARDMENT; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PHOTORESISTS; PROCESS CONTROL; QUALITY ASSURANCE; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTOR DEVICE MANUFACTURE;

CRITICAL DIMENSION VARIATION; LOGIC IMPLANT LAYERS; OPTICAL PROXIMITY CORRECTION; OVERLAY;

PHOTOLITHOGRAPHY;

EID: 0141834901     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.483691     Document Type: Conference Paper

References (1)

1. ITRS roadmap 2001