3D Stacked Packages with Bumpless Interconnect Technology

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2003, Pages 231-235

  Lin, Charles W C ^a   Chiang, Sam C L ^a   Yang, T K Andrew ^a  

^a Bridge Semiconductor Corporation   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; PRODUCT DESIGN; ROUTERS; ASSEMBLY; BONDING; CHEMICAL BONDS; CHIP SCALE PACKAGES; COPPER; ELECTRONICS PACKAGING; INDUSTRIAL ELECTRONICS; INTEGRATED CIRCUIT INTERCONNECTS; LEAD; MANUFACTURE; PACKAGING; PROCESS DESIGN; SPUTTERING; WIRE;

SOLDER BUMPS;

ELECTRONICS PACKAGING; THREE DIMENSIONAL INTEGRATED CIRCUITS;

BUMPLESS INTERCONNECT TECHNOLOGY; CHEMICAL PLATING; PACKAGING DENSITY; ROUTING; STACKING; VACUUM SPUTTERING; VERTICAL INTERCONNECTIONS; Z-AXIS INTERCONNECTS;

EID: 0141788720     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Lin, Charles W. C, Chiang, Sam C. L., Yang, T. K. Andrew, "Bumpless Flip Chip Packages For Cost/Performance Driven Devices," Proc Electronic Components and Technology Conference (ECTC), New Orleans, LA, May 2003.