Simulation meets verification-checking temporal properties in SystemC

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 2000, Pages 435-438

  Hoffmann, Dirk W ^a   Ruf, Jürgen ^a   Kropf, Thomas ^a   Rosenstiel, Wolfgang ^a  

^a UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED HARDWARE/SOFTWARE SYSTEMS; LEVELS OF ABSTRACTION; LINEAR TIME TEMPORAL LOGIC; SIMULATION-BASED METHOD; SYSTEM DESCRIPTION; TEMPORAL PROPERTY; VALIDATION AND VERIFICATION; VERIFICATION TECHNIQUES;

DESIGN; EMBEDDED SYSTEMS; HARDWARE; TESTING; VLSI CIRCUITS;

VERIFICATION;

EID: 0141779661     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.2000.874664     Document Type: Conference Paper

References (18)

1. D. Brand. Verification of Large Synthesized Designs. In IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, CA, November 1993. ACM/IEEE, IEEE Computer Society
2. J. Burch, E. Clarke, K. McMillan and D. Dill. Symbolic Model Checking: 1020 States and Beyond. In Proceedings of the Fifth Annual IEEE Symposium on Logic in Computer Science, pp. 1-33, Washington, D. C., June 1990. IEEE Computer Society, June 1990.
3. www. systemc. org
4. SystemC Reference Manual, Release 0. 9. Synopsys, Inc.
5. E. A. Emerson. Temporal and Modal Logic. In J. van Leeuwen, editor, Handbook of Theoretical Computer Science, volume B, pp. 9961072, Amsterdam, Elsevier Science Publishers, 1990.
6. www. verisity. com
7. Alexander Holt. Formal verification with natural language specifications: guidelines, experiments and lessons so far. In South African Computer Journal, No. 24, November 1999, pp. 253-257.
8. K. Schneider and D. Hoffmann. A HOL conversion for translating linear time temporal logic to CO-automata. In Higher Order Logic Theorem Proving and its Applications, LNCS, Nice, France, September 1999. Springer Verlag.
9. K. L. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, Norwell Masachusetts, 1993.
10. www. synopsys. com
11. www. cadence. com
12. www. mentor. com
13. W. C. Carter, W. H. Joyner Jr., and D. Brand. Symbolic simulation for correct machine design. In 16th ACM/IEEE Design Automation Conference (DAC), pp. 280-286, 1979
14. R. E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Transaction on Computers, C-35(8), August 1986
15. J. J. Joyce, and C.-J. H. Seger. Linking BDD based symbolic evaluation to interactive theorem proving. In Proceedings of the 30th Design Automation Conference (DAC), Dallas, TX, 1993
16. D. L. Dill. Tutorial on Symbolic Simulation. Conference for Computer Aided Verification (CAV), 1999, http://sprout. standford. edu/ talks. html.
17. D. L. Dill. Simulation Meets Formal Verification. International Conference on Computer Aided Design (ICCAD), 1999, http://sp-rout. standford. edu/talks. html.
18. J. R. Burch and D. L. Dill. Automatic Verification of Pipelined Microprocessor Control. In Proceedings of the International Conference on Computer Aided Design (ICCAD), LNCS 818, Springer, June 1994