A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 263-266

  Hsu, Cheng Chung ^a   Wu, Jieh Tsorng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CAPACITORS; WIRELESS TELECOMMUNICATION SYSTEMS;

CAPACITOR COUPLINGS;

CMOS INTEGRATED CIRCUITS;

EID: 0141761377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. T. Gratzek, et al, "A new paradigm for base station receivers: High IF sampling + digital filtering," IEEE Radio Frequency Integrated Circuits Symp., June 1997.
2. Wenhua Yang, et al, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE JSSC, December 2001.
3. J. A. Wepman, "Analog-to-digital converter technology comparison," IEEE Commun. Mag., May 1995.
4. K. Poulton, et al, "A 1-GHz 6-bit ADC system," IEEE JSSC, December 1987.
5. Peter J. Lim, et al, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE JSSC, April 1991.
6. P. Vorenkamp, et al, "Fully bipolar, 120 Ms/s 10 b track-and-hold circuit," IEEE JSSC, April 1992.
7. Andrea Boni, et al, "A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS," IEEE JSSC, February 2001.
8. K. Hadidi, et al, "An open-loop full CMOS 103MHz -61dB THD S/H circuit," in Proc. CICC, 1998.
9. K. Y. Kim, "A 10-bit, 100 MS/s analog-to-digital converter in 1μm. CMOS," Ph.D. thesis, Univ. Calif., Los Angeles, 1996
10. J. M. Ingino, et al, "A continuously calibrated 12-b, 10-MS/s, 3. 3-V A/D converter,"IEEE JSSC, December 1998.
11. W. C. Song, et al, "A 10-b 20-Msample/s low-power CMOS ADC," IEEE JSSC, May 1995.