Neuron-Synapse IC Chip-Set for Large-Scale Chaotic Neural Networks

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1393-1404

  Horio, Yoshihiko ^a   Aihara, Kazuyuki ^b   Yamamoto, O ^a  

^a TOKYO DENKI UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

Chaos; Chaotic neural networks; Large scale neural networks; Mixed analog digital system

Indexed keywords

CAPACITORS; CHAOS THEORY; CMOS INTEGRATED CIRCUITS; ELECTROPHYSIOLOGY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NEURAL NETWORKS;

NEURON CHIPS; SYNAPSE CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0141757101     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816349     Document Type: Article

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