A case for studying dram issues at the system level

IEEE Micro

Volumn 23, Issue 4, 2003, Pages 44-56

  Jacob, Bruce ^a,b  

^a UNIVERSITY OF MARYLAND   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CENTRAL PROCESSING UNIT; DELAY LOCKED LOOP; EXTENDED DATA OUT; FAST PAGE MODE; MEMORY SPEED;

BANDWIDTH; CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; INFORMATION TECHNOLOGY; INTERFACES (COMPUTER); MICROCOMPUTERS; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0141725665     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1225969     Document Type: Article

References (12)

1. R. Sites, "It's the Memory, Stupid!" Microprocessor Report, vol. 10, no. 10, Aug. 1996, pp. 1, 2.
2. S.A. McKee and W.A. Wulf, "Access Ordering and Memory-Conscious Cache Utilization," Proc. 1st IEEE Symp. High-Performance Computer Architecture (HPCA-1 95), IEEE CS Press, 1995, pp. 253-262.
3. J. Carter et al., "Impulse: Building a Smarter Memory Controller," Proc. 5th Int'l Conf. High-Performance Computer Architecture (HPCA-5 99), IEEE CS Press, 1999, pp. 70-79.
4. D. Burger, J.R. Goodman, and A. Kagi, "Memory Bandwidth Limitations of Future Microprocessors," Proc. 23rd Int'l Symp. Computer Architecture (ISCA 96), ACM Press, 1996, pp. 78-89.
5. A. Saulsbury, F. Pong, and A. Nowatzyk, "Missing the Memory Wall: The Case for Processor/Memory Integration," Proc. 23rd Int'l Symp. Computer Architecture (ISCA 96), ACM Press, 1996, pp. 90-101.
6. C. Kozyrakis et al., "Scalable Processors in the Billion-Transistor Era: IRAM," Computer, vol. 30, no. 9, Sept. 1997, pp. 75-78.
7. V. Cuppu and B. Jacob, "Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM System Performance?" Proc. 28th Int'l Symp. Computer Architecture (ISCA 01), IEEE CS Press, 2001, pp. 62-71.
8. V. Cuppu et al., "High Performance DRAMs in Workstation Environments," IEEE Trans. Computers, vol. 50, no. 11, Nov. 2001, pp. 1133-1153.
9. W.A. Wulf and S.A. McKee, "Hitting the Memory Wall: Implications of the Obvious," ACM Computer Architecture News, vol. 23, no. 1, Mar. 1995, pp. 20-24.
10. R.C. Schumann, "Design of the 21174 Memory Controller for Digital Personal Workstations," Digital Technical J., vol. 9, no. 2, 1997, pp. 57-70.
11. W.R. Bryg, K.K. Chan, and N.S. Fiduccia, "A High-Performance, Low-Cost Multiprocessor Bus for Workstations and Midrange Servers," Hewlett-Packard J., vol. 47, no. 1, Feb. 1996.
12. B. Davis et al., "DDR2 and Low Latency Variants," Proc. Memory Wall Workshop at the 26th Int'l Symp. Computer Architecture, 2000; http://www.ece.mfu.edu/faculty/btdavis/papers/mem_wall.isca2k.pdf.