On the relation between BDDs and FDDs

Information and Computation

Volumn 123, Issue 2, 1995, Pages 185-197

  Becker, Bernd ^a   Drechsler, Rolf ^a   Werchner, Ralph ^b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b GOETHE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0141684186     PISSN: 08905401     EISSN: 10902651     Source Type: Journal    
DOI: 10.1006/inco.1995.1167     Document Type: Article

References (49)

1. Ajtai, M., Babai, L., Hajnal, P., Komlos, J., Pudlak, P., Rodl, V., Szemeredi, E., and Turan, G. (1986), Two lower bounds for branching programs, in "Symposium on Theory of Computing," pp. 30-38.
2. Akers, S. B. (1978), Binary decision diagrams, IEEE Trans. Comput. C-27, 509-516.
3. Becker, B., and Drechsler, R. (1993), On the computational power of functional decision diagrams, in "20. Workshop uber Komplexitatstheorie, Datenstrukturen und effiziente Algorithmen, Berlin."
4. Becker, B., and Drechsler, R. (1994), Testability of circuits derived from functional decision diagrams, in "European Conference on Design Automation," p. 667.
5. Becker, B., and Drechsler, R. (1995), How many decomposition types do we need? in "European Design & Test Conference." pp. 438-443.
6. Becker, B., Drechsler, R. and Theobald, M. (1993), On the implementation of a package for efficient representation and manipulation of functional decision diagrams, in "IFIP WG 10.5 Workshop on Applications of the Reed -Muller Expansion in Circuit Design, Hamburg," pp. 162-169.
7. Becker, B., Drechsler, R. and Theobald, M. (1994), On variable ordering of ordered functional decision diagrams, in "GI/GME/ITG-Fachtagung Rechnergestiitzter Entwurf und Architektur mikroelektronisher Systeme," pp. 62-71, Springer-Verlag, Berlin/New York.
8. Berlekamp, E. R. (1968), "Algebraic Coding Theory," McGraw-Hill, New York.
9. Brglez, F., and Fujiwara, H. (1985), A neutral netlist of 10 combinational circuits and a target translator in Fortran, in "International Symposium on Circuits and Systems, Special Session on ATPG and Fault Simulation," pp. 663-698.
10. Brayton, R. K., Hachtel, G. D. McMullen, C., and Sangiovanni-Vincentelli, A. L. (1984), "Logic Minimization Algorithms for VLSI Synthesis," Kluwer Academic, Dordrecht/Norwell, MA.
11. Bryant, R. E. (1986), Graph-based algorithms for Boolean function manipulation, IEEE Trans. Comput. 8, 677-691.
12. Bryant, R. E. (1991), On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication, IEEE Trans. Comput. 40, 205-213.
13. Bryant, R. E. (1992), Symbolic boolean manipulation with ordered binary decision diagrams, ACM Comput. Surv. 24, 293-318.
14. Besslich, Ph. W., and Trachtenberg, E. A. (1992), A three-valued quasi-linear transformation for logic synthesis, in "Spectral Techniques: Theory and Applications" (C. Moraga and R. Creutzburg, Eds.), Elsevier, North Holland, Amsterdam.
15. Coudert, O., Fraisse, H. and Madre, J.-C. (1993), A breakthrough in two-level logic minimization, in "International Workshop on Logic Synthesis," pp. P2b.
16. Drechsler, R. and Becker, B. (1993), Rapid prototyping of fully testable multi-level AND/EXOR networks, in "IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Hamburg," pp. 126-133.
17. Drechsler, R. and Becker, B. (1995), Sympathy. Fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions, in "European Design & Test Conference," pp. 91-97.
18. Drechsler, R. Becker, B., and Gockel, N. (1995), A genetic algorithm for minimization of fixed polarity Reed-Muller expressions, in "International Conference on Artificial Neural Networks and Genetic Algorithms," pp. 392-395.
19. Drechsler, R. Sarabi, A., Theobald, M., Becker, B., and Perkowski, M. A. (1994), Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams, in "Design Automation Conference," pp. 415-419.
20. Drechsler, R. Theobald, M., and Becker, B. (1994), Fast OFDD based minimization of fixed polarity Reed-Muller expressions, in "European Design Automation Conference," pp. 2-7.
21. Gergov, J., and Meinel, C. (1992). Analysis and manipulation of boolean functions in terms of decision graphs, in "WG'92." pp. 310 320, Lecture Notes in Computer Science, Springer-Verlag, Berlin/New York.
22. Gergov, J., and Meinel, C. (1995), Efficient analysis and manipulation of OBDDs can be extended to FBDDs, IEEE Trans. CAD 43, 1197-1209.
23. Krieger, R. Becker, B., and Sinkovic, R. (1993), A BDD-based algorithm for computation of exact fault detection probabilities, in "International Symposium on Fault-Tolerant Computation," pp. 186-195.
24. Kebschull, U., and Rosenstiel, W. (1993), Efficient graph-based computation and manipulation of functional decision diagrams, in "European Conference on Design Automation," pp. 278-282.
25. Kebschull, U., Schubert, E., and Rosenstiel, W. (1992), Multilevel logic synthesis based on functional decision diagrams, in "European Conference on Design Automation," pp. 43-47.
26. Lee, C. Y. (1959), Representation of switching circuits by binary decision diagrams. Bell System Tech. J. 38, 985-999.
27. Van Leeuven, J., Ed. (1990), "Handbook of Theoretical Computer Science, Algorithms and Complexity," MIT Press, Cambridge, MA.
28. Lai, Y.-T., and Sastry, S. Edge-valued binary decision diagrams for multi-level hierarchical verification, in "Design Automation Conference," pp. 608-613.
29. Meinel, C. (1989), "Modified Branching Programs and Their Computational Power," Lecture Notes in Computer Science, Vol. 370, Springer-Verlag, Berlin/New York.
30. Minato, S. (1993), Zero-suppressed BDDs for set manipulation in combinational problems, in "Design Automation Conference," pp. 272-277.
31. Paterson, M. S. (1986), "On Razborov's Result for Bounded Depth circuits over (⊕, Δ)," Technical Report, University Warwick.
32. Pellerin, D. and Holley, M. (1991), "Practical Design Using Programmable Logic," Prentice-Hall, Englewood Cliffs, NJ.
33. Razborov, A. A. (1986), "Lower Bounds on the Size of Bounded Depth Networks over the Basis (⊕, Δ), Technical Report, Moscow State University. Moscow.
34. Reddy, S. M. (1972), Easily testable realizations for logic functions, IEEE Trans. Comput. C-21, pp. 1183-1188
35. Rollwage, U. (1993), The complexity of mod-2 sum PLA's for symmetric functions, in "IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Hamburg." pp. 6-12.
36. Rudell, R. (1993), Dynamic variable ordering for ordered binary decision diagrams, in "International Conference on CAD," pp. 42-47.
37. Sasao, T. (1993), "Logic Synthesis and Optimization," Kluwer Academic, Dordrecht/Norwell, MA.
38. Saul, J. (1992), Logic synthesis for arithmetic circuits using the Reed-Muller representation, in "European Conference on Design Automation," pp. 109-113.
39. Sasao, T., and Besslich, Ph. (1990). On the complexity of mod-2 sum PLAs, IEEE Trans. Comput. 39, 262-266.
40. Schubert, E., Kebschull, U., and Rosenstiel, W. (1992), FDD based technology mapping for FPGA, in "Proceedings of EUROASIC," pp. 14-18.
41. Sarabi, A., and Perkowski, M. A. (1993), Design for testability properties of and/or networks, in "IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Hamburg," pp. 147-153.
42. Saluja, K. K., and Reddy, S. M. (1975), Fault detection test sets for Reed Muller canonical networks," IEEE Trans. Comput. C-24, 995 -998.
43. Sieling, D. and Wegener, I. (1993), Reduction of BDDs in linear time. Inform. Process. Lett. 48 (3), 139-144.
44. Sieling, D. and Wegener, I. (1995), Graph driven BDDs A new data structure for Boolean functions, Theoret. Comput. Sci. 141, 283-310.
45. Wegener, I. (1984), Optimal decision trees and one-time-only branching programs for symmetric Boolean functions. Inform, and Control 62, 129-143.
46. Wegener, I. (1987), "The Complexity of Boolean Functions," Wiley, New York, Teubner, Stuttgart.
47. Werchner, R. Harich, T., Drechsler, R. and Becker, B. (1995), Satisfiability problems for ordered functional decision diagrams, in "IFIP WG 10.5 Workshop on Applications of the Reed Muller Expansion in Circuit Design, Chiba," pp. 206-212.
48. Wan, W., and Perkowski, M. A. (1992), A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to fpga mapping, in "European Design Automation Conference," pp. 230-235.
49. Xilinix Inc. (1988), "The Programmable Gate Array Data Book."