Clock Generation and Distribution for Intel Banias Mobile Microprocessor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 17-20

  Fayneh, Eyal ^a   Knoll, Ernest ^a  

^a MTM Scientific Industries Center   (Israel)

Author keywords

Clock distribution; Clock generation; Jitter; Microprocessor; Phase locked loop (PLL); Skew

Indexed keywords

ELECTRIC CLOCKS; ELECTRIC POWER SUPPLIES TO APPARATUS; PHASE LOCKED LOOPS; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS;

CLOCK GENERATION;

MICROPROCESSOR CHIPS;

EID: 0141649525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D Fletcher and P. D. Madland, "A Multi-GHz Clocking Scheme for Pentium® 4 Microprocessor", IEEE J. Solid-State Circuits, vol.36, pp 1647-1653, Nov. 2001
2. S. Tam, S. Rusu, U. N. Desai, R. Kim, Ji Zhang and I.A. Young, "Clock generation and Distribution for the First IA-64 Microprocessor", IEEE J. Solid-State Circuits, vol.35, pp 1545-1552, Nov.2000
3. K. L. Wong et al., "Cascaded PLL Design for a 90nm High Performance Microprocessor", ISSCC Digest of Technical Papers, 2003
4. I. A. Young, M. F. Mar, B. Bhushan, " A 0.35 mm CMOS 3-880MHz PLL N/2 Clock Multiplier and Distribution Network with Low Jitter for Microprocessors", ISSCC Digest of Technical Papers, 1997