A novel 64-point FFT/IFFT processor for IEEE 802.11(A) standard

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 2, Issue , 2003, Pages 321-324

  Maharatna, K ^a   Grass, E ^a   Jagdhold, U ^a  

^a IHP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE;

DIGITAL MULTIPLIERS;

MOBILE TELECOMMUNICATION SYSTEMS;

EID: 0141590268     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. IEEE P802.11a/D7.0, "Draft supplement to standard [for] information technology-telecommunications and information exchange between systems - local and metropolitan area networks-specific requirements - Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High speed physical layer in the 5 GHz band".
2. E. Grass, K. Tittelbach, U. Jagdhold, A. Troya, G. Lippert, O. Krueger, J. Lehmann, K. Maharatna, N. Fiebig, K. Dombrowski, R. Kraemer, P. Maehoenen, "On the Single Chip Implementation of a Hiperlan/2 and IEEE802.11a Capable Modem", IEEE Personal Communication, vol. 8, no. 6, pp. 48 - 57, December 2001.
3. J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series", Math. Computation, vol. 19, pp. 297 - 301, 1965.
4. Xilinx Product Specification, "High-performance 64-point complex FFT/IFFT V1.0.5", http://www.xilinx.com/ipcenter.
5. Altera Megafunction technical brief, "ISS High-performance 64-point FFT/IFFT", http://www.spinnaker.co.jp/jp/datasheet/tb_fft_1_V002.pdf.
6. Icomm Technologies Inc. Product design data sheet, "FFT-1024 complex 1024-points FFT/IFFT processor".
7. M3 Architecture Specification Rev. 1.3: Functional Specification, Technishe Universitaet, Dresden, 1999.
8. J. V. McCanny, D. Trainor, Y. Hu and T. J. Ding, "Rapid design of complex DSP cores", http://www.esscirc.org/papers-97/102.pdf.
9. T. Chen and L. Zhu, "An expandable column FFT architecture using circuit switching network", Journal of VLSI Signal Processing, Jan. 1994.
10. T. Chen, G. Sunanda and J. Jin, "COBRA: A 100-MOPS Single-Chip Programmable and Expandable FFT", IEEE Trans. VLSI, vol. 7, no. 2, June 1999.