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Volumn 2002-January, Issue , 2002, Pages 266-273

Towards an artificial neural network framework

Author keywords

Application specific integrated circuits; Artificial neural networks; Digital circuits; Field programmable gate arrays; Network topology; Neural network hardware; Neural networks; Neurons; Scalability; Signal processing

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENETIC ALGORITHMS; HARDWARE; NASA; NETWORKS (CIRCUITS); NEURONS; SCALABILITY; SIGNAL PROCESSING;

EID: 0141466861     PISSN: 15506029     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.2002.1029893     Document Type: Conference Paper
Times cited : (11)

References (10)
  • 2
    • 0011770034 scopus 로고    scopus 로고
    • Perspectives on dedicated hardware implementations
    • D-Facto
    • D. Anguita and M. Valle. Perspectives on dedicated hardware implementations. In Proceedings ESANN 2001, pages 45-55. D-Facto, 2001.
    • (2001) Proceedings ESANN 2001 , pp. 45-55
    • Anguita, D.1    Valle, M.2
  • 3
    • 84949244673 scopus 로고    scopus 로고
    • February XAPP140
    • H. Agah. Physical Synthesis. Xilinx, Inc, www.xilinx.com, February 2001. XAPP140.
    • (2001) Physical Synthesis
    • Agah, H.1
  • 6
    • 84955596039 scopus 로고    scopus 로고
    • A VLSI implementation of an analog neural network suited for genetic algorithms
    • Springer Verlag
    • J. Schemmel, K. Meier, and F. Schürmann. A VLSI implementation of an analog neural network suited for genetic algorithms. In Proceedings ICES 2001, pages 50-61. Springer Verlag, 2001.
    • (2001) Proceedings ICES 2001 , pp. 50-61
    • Schemmel, J.1    Meier, K.2    Schürmann, F.3
  • 7
    • 0036086769 scopus 로고    scopus 로고
    • An integrated mixed-mode neural network architecture for megasynapse ANNs
    • Accepted for presentation Honolunu (Hawaii, USA), May
    • J. Schemmel, F. Schürmann, S. Hohmann, and K. Meier. An integrated mixed-mode neural network architecture for megasynapse ANNs. Accepted for presentation at IJCNN 2002, Honolunu (Hawaii, USA), May 2002.
    • (2002) IJCNN 2002
    • Schemmel, J.1    Schürmann, F.2    Hohmann, S.3    Meier, K.4
  • 8
    • 0141801674 scopus 로고    scopus 로고
    • Exploring the parameter space of a genetic algorithm for training an analog neural network
    • Accepted for presentation New York (USA)
    • S. Hohmann, J. Schemmel, F. Schürmann, and K. Meier. Exploring the parameter space of a genetic algorithm for training an analog neural network. Accepted for presentation at GECCO 2002, New York (USA), 2002.
    • (2002) GECCO 2002
    • Hohmann, S.1    Schemmel, J.2    Schürmann, F.3    Meier, K.4
  • 9
    • 0033717370 scopus 로고    scopus 로고
    • A VLSI architecture for weight perturbation on chip learning implementation
    • F. Diotalevi, M. Valle, G. Bo, and D. Caviglia. A VLSI architecture for weight perturbation on chip learning implementation. In Proceedings IJCNN 2000, volume IV, pages 219-224, 2000.
    • (2000) Proceedings IJCNN 2000 , vol.4 , pp. 219-224
    • Diotalevi, F.1    Valle, M.2    Bo, G.3    Caviglia, D.4
  • 10
    • 0031632183 scopus 로고    scopus 로고
    • Hardware realization of a hamming neural network with on-chip learning
    • A. Schmid, Y. Leblebici, and D. Mlynek. Hardware realization of a hamming neural network with on-chip learning. In Proceedings ISCAS 1998, 1998.
    • (1998) Proceedings ISCAS 1998
    • Schmid, A.1    Leblebici, Y.2    Mlynek, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.