Wire Bond Short Reduction by Encapsulation

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2003, Pages 55-58

  Hmiel, Andrew F ^a   Rutiser, Claire ^a  

^a Kulicke and Soffa   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; RHEOLOGY; SURFACE TENSION; WIRE; AUTOMATION; CHIP SCALE PACKAGES; CONTROL; ELASTICITY; ENCAPSULATION; FILLED POLYMERS; INDUSTRIAL ELECTRONICS; MANUFACTURE; PHYSICS; POLYMERS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; TESTING;

MULTIPLE LAYERS;

ELECTRONICS PACKAGING;

AUTOMATED METHODS; COMMERCIAL CHALLENGES; ELECTRICAL TESTS; MULTIPLE LAYERS; PACKAGING PROCESS; SEMICONDUCTOR DEVICE PACKAGING; SEMICONDUCTOR PACKAGING; ULTRA FINE PITCH;

EID: 0141453878     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. rd Semiconductor Packaging Symp., SEMICON West, San Jose CA, July 2000, pp. D-1 - D17.
2. C. D. Dushkin, P. A. Kralchevsky, H. Yoshimura and N. Nagayams, Phys. Rev. Lett. Vol. 75, 19, 6 Nov. 1995