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Volumn , Issue , 2003, Pages 401-407
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Process Challenges in Low-k Wafer Dicing
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Author keywords
[No Author keywords available]
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Indexed keywords
CHEMICAL VAPOR DEPOSITION;
ELECTRONICS PACKAGING;
INTEGRATED CIRCUITS;
PERMITTIVITY;
CHEMISTRY;
CHIP SCALE PACKAGES;
ELECTRONICS INDUSTRY;
INDUSTRIAL ELECTRONICS;
MANUFACTURE;
MATERIALS PROPERTIES;
PACKAGING MATERIALS;
SAWING;
SEMICONDUCTOR DEVICE MANUFACTURE;
SEMICONDUCTOR DEVICES;
SEMICONDUCTOR MATERIALS;
SILICON WAFERS;
WAFER DICING;
SEMICONDUCTOR DEVICE MANUFACTURE;
DIELECTRIC MATERIALS;
DEVICE RELIABILITY;
INTERCONNECT PERFORMANCE;
LOW DIELECTRIC CONSTANTS;
LOW-K DIELECTRIC MATERIALS;
MANUFACTURING PROCESS;
PROCESS INTEGRATION;
SEMICONDUCTOR DEVICE PACKAGING;
SEMICONDUCTOR INDUSTRY;
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EID: 0141453803
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (13)
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References (4)
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