10 GHz, 20mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a .18μm digital CMOS process

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 181-184

  Ravi, A ^a   Banerjee, G ^a   Bishop, R E ^a   Bloechel, B A ^a   Carley, L R ^a   Soumyanath, K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; ELECTRIC POWER SYSTEMS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; SIGNAL DETECTION; VARIABLE FREQUENCY OSCILLATORS;

AGILE FREQUENCY SYNTHESIS;

CMOS INTEGRATED CIRCUITS;

EID: 0141426711     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Ravi et al, Proc of ESSCIRC, 2002.
2. D. G. Messerschmidt et al, IEEE TCOM, pp 1288-1295, Sep. 1979.
3. A. Pottbacker et al, IEEE JSSC, vol. SC-27, pp 1747-1751, Dec. 1992.