-
1
-
-
0018294137
-
Optical computation using residue arithmetic
-
A. Huang, Y. Tsunida, J. W. Goodman, and S. Ishihara, "Optical computation using residue arithmetic," Appl. Opt. 18, 149-162 (1979).
-
(1979)
Appl. Opt.
, vol.18
, pp. 149-162
-
-
Huang, A.1
Tsunida, Y.2
Goodman, J.W.3
Ishihara, S.4
-
2
-
-
84975603547
-
Optical binary coded ternary arithmetic and logic
-
G. Eichmann, Y. Li, and R. R. Alfano, "Optical binary coded ternary arithmetic and logic," Appl. Opt. 25, 3113-3121 (1986).
-
(1986)
Appl. Opt.
, vol.25
, pp. 3113-3121
-
-
Eichmann, G.1
Li, Y.2
Alfano, R.R.3
-
3
-
-
0022439670
-
Multiple-valued logic: An implementation
-
T. T. Dao and D. M. Campbell, "Multiple-valued logic: an implementation," Opt. Eng. 25(1), 14-21 (1986).
-
(1986)
Opt. Eng.
, vol.25
, Issue.1
, pp. 14-21
-
-
Dao, T.T.1
Campbell, D.M.2
-
4
-
-
0021609266
-
Multiple valued logic - Its status and its future
-
S. L. Hurst, "Multiple valued logic - its status and its future," IEEE Trans. Comput. C-33, 1160-1179 (1984).
-
(1984)
IEEE Trans. Comput.
, vol.C-33
, pp. 1160-1179
-
-
Hurst, S.L.1
-
5
-
-
0018507382
-
Optical residue arithmetic computer with programmable computation modules
-
A. Tai, I. Cindrich, J. R. Fienup, and C. C. Aleksoff, "Optical residue arithmetic computer with programmable computation modules," Appl. Opt. 18, 2812-2823 (1979).
-
(1979)
Appl. Opt.
, vol.18
, pp. 2812-2823
-
-
Tai, A.1
Cindrich, I.2
Fienup, J.R.3
Aleksoff, C.C.4
-
6
-
-
84937078021
-
Signed-digit number representation for fast parallel arithmetic
-
A. Avizienis, "Signed-digit number representation for fast parallel arithmetic," IRE Trans. Electron. Comput. EC-10, 389-400 (1961).
-
(1961)
IRE Trans. Electron. Comput.
, vol.EC-10
, pp. 389-400
-
-
Avizienis, A.1
-
7
-
-
0022440053
-
Photonic computing using modified signed-digit number representation
-
B. L. Drake, R. P. Bocker, M. E. Lasher, R. H. Petterson, and W. J. Miceli, "Photonic computing using modified signed-digit number representation," Opt. Eng. 25(1), 38-43 (1986).
-
(1986)
Opt. Eng.
, vol.25
, Issue.1
, pp. 38-43
-
-
Drake, B.L.1
Bocker, R.P.2
Lasher, M.E.3
Petterson, R.H.4
Miceli, W.J.5
-
8
-
-
84975598459
-
Bit error rate optical logic: Fan-in, threshold, and contrast
-
C. W. Stirk, "Bit error rate optical logic: fan-in, threshold, and contrast," Appl. Opt. 31, 5632-5641 (1992).
-
(1992)
Appl. Opt.
, vol.31
, pp. 5632-5641
-
-
Stirk, C.W.1
-
9
-
-
0028459529
-
Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor
-
B. Ha and Y. Li, "Parallel modified signed-digit arithmetic using an optoelectronic shared content-addressable-memory processor," Appl. Opt. 33, 3647-3662 (1994).
-
(1994)
Appl. Opt.
, vol.33
, pp. 3647-3662
-
-
Ha, B.1
Li, Y.2
-
10
-
-
0001037786
-
Introduction to a general theory of elementary propositions
-
E. L. Post, "Introduction to a general theory of elementary propositions," Am. J. Math. 43, 163-185 (1921).
-
(1921)
Am. J. Math.
, vol.43
, pp. 163-185
-
-
Post, E.L.1
-
12
-
-
0022544738
-
Multiple-valued threshold logic: Its status and its realization
-
S. L. Hurst, "Multiple-valued threshold logic: its status and its realization," Opt. Eng. 25(1), 44-56 (1986).
-
(1986)
Opt. Eng.
, vol.25
, Issue.1
, pp. 44-56
-
-
Hurst, S.L.1
-
13
-
-
0042314800
-
A CMOS current-mode full adder cell for multi-valued logic VLSI
-
Naval Postgraduate School, Monterey, CA
-
R. J. Barton III, T. O. Walker III, and D. J. Fouts, "A CMOS current-mode full adder cell for multi-valued logic VLSI," Department of Electrical and Computer Engineering Report, Naval Postgraduate School, Monterey, CA.
-
Department of Electrical and Computer Engineering Report
-
-
Barton R.J. III1
Walker T.O. III2
Fouts, D.J.3
-
15
-
-
0001146101
-
A signed binary multiplicalion technique
-
A. D. Booth, "A signed binary multiplicalion technique," Q. J. Mech. Appl. Math. 4(2), 236-240 (1951).
-
(1951)
Q. J. Mech. Appl. Math.
, vol.4
, Issue.2
, pp. 236-240
-
-
Booth, A.D.1
-
16
-
-
0026867192
-
Towards the realization of 4 valued CMOS circuits
-
L. Konreid and G. Z. Vranesic, "Towards the realization of 4 valued CMOS circuits," in Proc. 22nd ISMVL, p. 106 (1992).
-
(1992)
Proc. 22nd ISMVL
, pp. 106
-
-
Konreid, L.1
Vranesic, G.Z.2
-
17
-
-
0003663466
-
-
Chaps. 4 and 5, McGraw-Hill, New York
-
P. Z. Peebles, Probability, Random Variables, and Random Signal Principles, Chaps. 4 and 5, McGraw-Hill, New York (1987).
-
(1987)
Probability, Random Variables, and Random Signal Principles
-
-
Peebles, P.Z.1
-
18
-
-
84975633479
-
Noise limitations in optical linear algebra processors
-
S. G. Barsell, T. L. Jong, J. F. Walkup, and T. F. Krile, "Noise limitations in optical linear algebra processors," Appl. Opt. 29, 2084-2090 (1990).
-
(1990)
Appl. Opt.
, vol.29
, pp. 2084-2090
-
-
Barsell, S.G.1
Jong, T.L.2
Walkup, J.F.3
Krile, T.F.4
-
19
-
-
0028738322
-
How large can an optical matrix-matrix multiplier be constructed?
-
Y. Li and B. Ha, "How large can an optical matrix-matrix multiplier be constructed?," Proc. SPIE 2240, 132-143 (1995).
-
(1995)
Proc. SPIE
, vol.2240
, pp. 132-143
-
-
Li, Y.1
Ha, B.2
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