RNS-modulo reduction upon a restricted base value set and its applicability to RSA cryptography

Computers and Security

Volumn 17, Issue 7, 1998, Pages 637-650

  Schwemmlein, J ^a   Posch, K C ^b   Posch, R ^b  

^a AMS AG   (Austria)

^b GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Computer arithmetic; Cryptography; Long integer arithmetic; Modulo reduction; Parallel algorithms; Public key; Residue number systems; VLSI

Indexed keywords

EID: 0043265955     PISSN: 01674048     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-4048(99)80061-3     Document Type: Article

References (10)

1. D. E. Knuth, The art of computer programming, Seminumerical Algorithms, Vol. 2, second edition, Addison Wesley, 1981.
2. H. Lüneburg, Vorlesungen über Zahlentheorie, Elemente der Mathematik vom höheren Standpunkt aus, Band VIII, ed. E. Trost, Birkhäuser Verlag, 1978.
3. P. L. Montgomery, Modular multiplication without trial division, Mathematics of Computation, 44 (1985) 519-521.
4. K. C. Posch and R. Posch, Base extension using a convolution sum in residue number systems. Computing, Springer Verlag, Vol. 50, 1993, pp. 93-104.
5. K. C. Posch and R. Posch, Modulo reduction in residue number systems, IEEE Transactions on Parallel and Distributed Systems Vol. 6, No. 5, May 1995, pp. 449-454.
6. K. C. Posch and R. Posch, Residue number systems: a key to parallelism in public key cryptography, Fourth IEEE Symposium on Parallel and Distributed Processing, Dallas, Dec. 1992.
7. R. L. Rivest, A. Shamir and L. Adleman, A method for obtaining digital signatures and public key systems, Communications of the ACM, 21 (1978) 120-126.
8. A. P. Shenoy and R. Komaresan, Fast base extension using a redundant modulus in RNS, IEEE Transactions on Computers, 38 (1989) 292-297.
9. J. Schwemmlein, K. C. Posch and R. Posch, High performance modular arithmetic using an RNS based chipset, Proceedings of the 1st Conference on Massively Parallel Computing Systems, Ischia, 1994, pp. 444-451.
10. C. S. Wallace, A suggestion for a fast multiplier, IEEE Transactions on Electronic Computers, EC-13, 1964, pp. 14-17.