RAPTOR: A single chip multiprocessor

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 217-220

  Lee, Sang Won ^a   Song, Yun Seob ^a   Kim, Soo Won ^a   Oh, Hyeong Cheol ^a   Hahn, Woo Jang ^b  

^a Korea University   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0043207939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824067     Document Type: Conference Paper

References (13)

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4. Matthias Bauer and Wolfgang Ecker, "Hardware/Software Co-Simulation in a VHDL-based Test Bench Approach, " DAC'97, Anaheim, California, Jun 9-13, 1997.
5. Ricardo Bianchini and Thomas J. LeBlanc, "Eager Combining: A Coherency Protocol for Increasing Effective Network and Memory Bandwidth in Shared-Memory Multiprocessors, " Technical Report 485, Computer Science Department, The University of Rochester, Rochester, New York, January, 1994.
6. L. Gwennap, " Microprocessors head toward MP on a chip, " Microprocessor report, Vol. 8, No. 6, pp. 18-21, May 1994.
7. Lance Hammond, Basem A. Nayfeh and Kunle Olukotun, "A Single-Chip Multiprocessor, " IEEE Computer, September 1997.
8. David A. Patterson, John L. Hennessy, Computer Architecture A Quantitative Approach, 2nd Ed., Morgan Kaufmann Publishers, Inc., 1996.
9. David Culler, Jaswinder P. Singh, Anoop Gupta, Parallel Computer Architecture : A Hardware/Software Approach, Draft, Morgan Kaufmann, 1997.
10. David L. Weaver, Tom Germond, The SPARC Architecture Manual Ver. 9, SPARC International Inc., Prentice Hall, 1994.
11. UltraSPARC-I User's Manual, Sun Microsystems, Inc., 1995.
12. The UltraSPARC Processor-The UltraSPARC Architecture, Technology Whitepaper, Sun Microelectronics, Inc., 14, Nov, 1995.
13. Ultra Port Architecture (UPA): The New-Media System Architecture, Whitepaper 95-023, Sun Microelectronics, Inc.