A pipelined architecture for ray/Bézier patch intersection computation

Canadian Journal of Electrical and Computer Engineering

Volumn 28, Issue 1, 2003, Pages 27-35

  Lewis, Robert R ^a   Wang, Renwei ^a   Hung, Donald ^b  

^a WASHINGTON STATE UNIVERSITY   (United States)

^b SAN JOSE STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEZIER PATCH INTERSECTION COMPUTATION; RAY PATCH INTERSECTION COMPUTATION;

ALGORITHMS; COMPUTATIONAL GEOMETRY; DATA HANDLING; DIGITAL SIGNAL PROCESSING; MAXIMUM PRINCIPLE; RAY TRACING;

PIPELINE PROCESSING SYSTEMS;

EID: 0042942871     PISSN: 08408688     EISSN: None     Source Type: Journal    
DOI: 10.1109/CJECE.2003.1426071     Document Type: Article

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