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Volumn 24, Issue 7, 2003, Pages 472-474

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics

Author keywords

Atomic layer deposition; Hole mobility; Id Vd characteristics; p MOSFET; Si nitride; Stack gate dielectrics

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DIELECTRIC DEVICES; ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); MOSFET DEVICES; NANOTECHNOLOGY; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICA;

EID: 0042888791     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.814015     Document Type: Letter
Times cited : (5)

References (15)
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  • 7
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  • 8
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    • Ultra thin (<3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing
    • B. Y. Kim, H. F. Luan, and D. L. Kwong, "Ultra thin (<3 nm) high quality nitride/oxide stack gate dielectrics fabricated by in-situ rapid thermal processing," in IEDM Tech. Dig., 1997, pp. 463-466.
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    • Kim, B.Y.1    Luan, H.F.2    Kwong, D.L.3
  • 14
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    • MOS capacitance measurements for high-leakage thin dielectrics
    • July
    • K. J. Yang and C. Hu, "MOS capacitance measurements for high-leakage thin dielectrics," IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, July 1999.
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    • Yang, K.J.1    Hu, C.2
  • 15
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    • Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
    • Nov.
    • K. Chen, C. Hu, P. Fang, M. R. Lin, and D. L. Wollesen, "Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects," IEEE Trans. Electron Devices, vol. 44, pp. 1951-1957, Nov. 1997.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.