Inference of message sequence charts

IEEE Transactions on Software Engineering

Volumn 29, Issue 7, 2003, Pages 623-633

  Alur, Rajeev ^a   Etessami, Kousha ^b   Yannakakis, Mihalis ^c  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

^b UNIVERSITY OF EDINBURGH   (United Kingdom)

^c Stanford University   (United States)

Author keywords

Concurrent state machines; Deadlock freedom; Formal verification; Message sequence charts; Realizability; Requirements analysis; Scenarios; Synthesis

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; CONCURRENT ENGINEERING; DISTRIBUTED COMPUTER SYSTEMS; INFERENCE ENGINES; POLYNOMIALS; SET THEORY; TELECOMMUNICATION; THEOREM PROVING;

CONCURRENT STATE MACHINES; CONCURRENT SYSTEMS; MESSAGE SEQUENCE CHARTS;

SOFTWARE ENGINEERING;

EID: 0042850360     PISSN: 00985589     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSE.2003.1214326     Document Type: Article

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