Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions

IEEE Electron Device Letters

Volumn 24, Issue 5, 2003, Pages 342-344

  Vandooren, A ^a   Barr, A ^a   Mathew, L ^a   White, T R ^a   Egley, S ^a   Pham, D ^a   Zavala, M ^a   Samavedam, S ^a   Schaeffer, J ^a   Conner, J ^a   Nguyen, B Y ^a   White Jr , Bruce E ^a   Orlowski, Marius K ^a   Mogab, J ^a  

^a MOTOROLA INC   (United States)

Author keywords

CMOSFETs; High K; Metal gate; Silicon on insulator technology

Indexed keywords

EPITAXIAL GROWTH; ETCHING; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; TANTALUM COMPOUNDS; THERMOOXIDATION; THRESHOLD VOLTAGE; ULTRATHIN FILMS; VOLTAGE CONTROL;

FILM THICKNESS; HAFNIUM DIOXIDE GATE DIELECTRIC; SOURCE-DRAIN EXTENSION REGION; THRESHOLD VOLTAGE CONTROL;

MOSFET DEVICES;

EID: 0042674226     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.812525     Document Type: Article

References (10)

1. M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, and H. Tango, "Two-dimensional simulation and measurement of high-performance MOSFET's made on a very thin SOI film," IEEE Trans. Electron Devices, vol. 36, pp. 493-503, Mar. 1989.
2. R. Koh, "Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI MOSFET," Jpn. J. Appl. Phys., vol. 38, pp. 2294-2299, 1999.
3. J. Chen, B. Maiti, D. Connelly, M. Mendicino, F. Huang, O. Adetutu, Y. Yu, D. Weddington, W. Wu, J. Candelaria, D. Dow, P. Tobin, and J. Mogab, "0.18 μm metal gate fully depleted SOI MOSFET's for advanced CMOS applications," in VLSI Tech. Dig., 1999, pp. 25-26.
4. H. Shimada, Y. Hirano, T. Ushiki, K. Ino, and T. Ohmi, "Tantalum-gate thin film SOI nMOS and pMOS for low power applications," IEEE Trans. Electron Devices, vol. 44, pp. 1903-1907, Nov. 1997.
5. 2) dielectric and elevated source/drain extensions," in IEEE SOI Int. Conf., Oct. 7-10, 2002, pp. 205-206.
6. 2 gate dielectric," in VLSI Tech. Dig., 2002, pp. 24-25.
7. J. Chen, R. Solomon, T.-Y. Chan, P. K. Ko, and C. Hu, "A CV technique for measuring thin SOI film thickness," IEEE Electron Device Lett., vol. 12, pp. 453-445, Aug. 1991.
8. M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, "SOI MOSFET effective channel mobility," IEEE Trans. Electron Devices, vol. 41, pp. 276-278, Feb. 1994.
9. G. Ghibaudo, "New method for the extraction of MOSFET parameters," Electron. Lett., vol. 24, pp. 543-543, 1988.
10. T. Ouisse, S. Cristoloveanu, and G. Borel, "Influence of series resistances and interface coupling on the transconductance of fully-depleted silicon-on-insulator MOSFET's," Solid-State Electron., vol. 35, pp. 141-141, 1992.