Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter

Optical Engineering

Volumn 35, Issue 6, 1996, Pages 1785-1793

  Chen, Ray T ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Modified signed digit adder and subtractor; Optoelectronic switch and interconnect technologies; Parallel algorithm; Parallel architecture; Space position logic encoding

Indexed keywords

EID: 0041814222     PISSN: 00913286     EISSN: None     Source Type: Journal    
DOI: 10.1117/1.600752     Document Type: Article

References (3)

1. A. Avizienis, "Signed-digit number representations for fast parallel arithmetic," IRE Trans. Electron. Comput. EC-10, 389-398 (1961).
2. B. L. Drake, R. P. Bocker, M. E. Lasher, R. H. Patterson, and W. J. Miceli, "Photonic computing using the modified-digit number representation," Opt. Eng. 25, 38-43 (1986).
3. K. Hwang and A. Louri, "Optical multiplication and division using modified-signed-digit symbolic substitution," Opt. Eng. 28, 364-372 (1989).