Experimenting with new cleaning technologies for use in semiconductor manufacturing

MICRO

Volumn 20, Issue 4, 2002, Pages 33-40

  Small, Robert J ^a   Lee, Shihying ^b   Finson, Eric ^a   Maloney, David ^a  

^a CMP group   (United States)

^b EKC Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0041790742     PISSN: 10810595     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

1. A Hand, "Wafer Cleaning Confronts Increasing Demands," Semiconductor International 24, no. 8 (2001): 62-65.
2. R Dejule, "A Move to Single Wafer Cleaning," Solid State Technology Web page exclusive [cited November 6, 2001]; available from Internet: www.solid-state.com.
3. TS Roche and TW Peterson, "Reducing DI Water Use," Solid State Technology Web page [cited December 1996]; available from Internet: www.solid-state.com.
4. EKC Technology technical data (Danville, CA: EKC Technology).
5. D Deal, "Coming Clean: What's Ahead in Silicon Wafer Cleaning Technology," Precision Cleaning II, no. 6 (1994): 24-30.
6. RM Hall et al., "Improving Rinse Efficiency with Automated Cleaning Tools," Semiconductor International 19, no. 12 (1996): 151-160.
7. G Corlett, "CMP Water Reduction and Waste Treatment Overview," in Proceedings of CMP Technology for ULSI Interconnect Symposium (Mountain View, CA: SEMI, 1998), Ql-Qll.
8. J Diedrick et al., "Improved Post-Etch Via Clean with Fluoride-Based Semi-Aqueous Chemistry Using an Intermediate Rinse" (paper presented at the Electrochemical Society Meeting, San Francisco, September 2-7, 2001).
9. R Small et al., "Investigating the Two Part Cleaning Process With Semi-Aqueous Fluoride Chemistry" (paper presented at the VMIC Conference, Santa Clara, CA, September 25-26, 2001).
10. A Tonti, "A Simple Model for Rinsing," in Proceedings of the Second International Symposium on Cleaning Technology in Semiconductor Device Manufacturing (Pennington, NJ: Electrochemical Society, 1992), 41-47.
11. J Rosato et al., "Studies of Rinse Efficiencies in Wet Cleaning Tools," in Proceedings of Cleaning Technology in Semiconductor Device Manufacturing (Pennington, NJ: Electrochemical Society, 1994), 140-152.
12. D Louis et al., "Improved Post Etch Cleaning for Low-k and Copper Integration for 0.18-μm Technology," Microelectronic Engineering 46, no 1 (1999): 307-310.
13. D Louis et al., "Post Etch Cleaning of Dual Damascene System Integrating Copper and SiLK, in Proceedings of the IEEE International Interconnect Technology Conference (Piscat-away, NJ: IEEE, 1999), 103-105.
14. J Waeterloos et al., "Damascene Integration Feasibility of Developmental Porous SiLK Resin Film" (paper presented at the Advanced Metallization Conference, Montreal, Canada, October 9-10, 2000).