Direct measurement of residual stress in integrated circuit interconnect features

Microelectronics Reliability

Volumn 43, Issue 9-11, 2003, Pages 1797-1801

  Horsfall, A B ^a   Dos Santos, J M M ^a   Soare, S M ^a   Wright, N G ^a   O'Neill, A G ^a   Bull, S J ^a   Walton, A J ^b   Gundlach, A M ^b   Stevenson, J T M ^b  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; RESIDUAL STRESSES; SINTERING;

STRESS SENSORS;

INTEGRATED CIRCUITS;

EID: 0041692471     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(03)00306-8     Document Type: Conference Paper

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