An all-digital frequency locked loop (ADFLL) with a pulse output direct digital frequency synthesizer (DDFS) and an adaptive phase estimator

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2003, Pages 303-306

  Gothandaraman, Akila ^a   Islam, Syed K ^a  

^a University of Tennessee Knoxville   (United States)

Author keywords

All digital Phase Locked Loops (ADPLLs); Frequency synthesizer; Phase locked loop

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; COSTS; FREQUENCIES; FREQUENCY SYNTHESIZERS; PHASE LOCKED LOOPS;

ADAPTIVE PHASE ESTIMATOR;

DIGITAL SIGNAL PROCESSING;

EID: 0041589146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Thomas H.Lee, The Design of CMOS Radio Frequency Integrated Circuits: Cambridge University Press, 1998.
2. Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee, "An All-Digital Phase Locked Loop (ADPLL) - Based Clock Recovery Circuit," IEEE J. Solid-State Circuits, vol. 34, pp. 1063-1073, August 1999.
3. Jouko Vankka, Direct Digital Synthesizers: Theory, Design and Applications: Kluwer Academic Publishers, 2001.
4. Analog Devices Inc., A Technical Tutorial on Direct Digital Synthesis, " Analog Devices Inc.
5. Jim Dunning, Gerald Garcia, Jim Lundberg, and Ed Nuckolls, "An All-Digital Phase-Locked Loop with 50-cycle lock time suitable for High-Performance Microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp. 412-422, April 1995.