Optimal Chaining of CMOS Transistors in a Functional Cell

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 5, 1987, Pages 795-801

  Wimer, Shmuel ^a   Pinter, Ron Y ^a   Feldman, Jack A ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0041476339     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270322     Document Type: Article

References (10)

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8. R. Nair, A Bruss, and J. Reif, “Linear time algorithms for optimal CMOS layout,” in VLSI: Algorithms and Architectures, P. Bertolazzi and F. Luccio, Eds. New York: Elsevier North-Holland, 1985, pp. 327–338.
9. R. L. Rivest and C. M. Fiduccia, “A ‘Greedy’ channel router,” in Proc. 19th Design Automat. Conf., June 1982, pp. 418–424.
10. T. Uehara and W. M. van Cleemput, “Optimal layout of CMOS functional arrays,” IEEE Trans. Comput., vol. C-30, 5, pp. 305–312, May 1981.