A monolithic CMOS 10.4-GHz phase locked loop

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 36-37

  Yang, Dong Jun ^a   Kenneth, O ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; FEEDBACK CONTROL; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS; VOLTAGE MEASUREMENT;

DUAL MODULUS PRESCALER; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 0041383789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Floyd M. Gardner, IEEE transactions on Communication Electronics, pp. 1849-1858, November 1980.
2. C.-M. Hung and O K.K. IEEE J. of Solid-State Circuits, vol. 35, no. 1, pp. 100-103, Jan. 2000.
3. N.-K. Park, and K. K. O, accepted to 16th Intl. Conf. on Noise in Physical Systems and 1/f Fluctuations.
4. Dan H. Wolaver, Phase-Looked Loop Circuit Design, NJ:Prentice-Hall 1991.