Performance of a context cache for a multithreaded pipeline

Journal of Systems Architecture

Volumn 45, Issue 4, 1998, Pages 305-322

  Omondi, Amos R ^a   Horne, Michael ^b  

^a FLINDERS UNIVERSITY   (Australia)

^b EDS 68 Jervois Quay ^*  (New Zealand)

Author keywords

Context cache; Instruction pipeline; Microthreading; Multithreading; Renaming

Indexed keywords

EID: 0041357268     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(97)00084-2     Document Type: Article

References (16)

1. R. Alverson, The TERA computer system, in: Proc. International Symposium on Supercomputing, ACM, New York, 1990, pp. 1-6.
2. J.B. Dennis, G.R. Gao, Multithreaded architectures: Principles, projects, and issues, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 1-72.
3. A. Bolychevsky, C.R. Jesshope, V.B. Muchnik, Dynamic scheduling in a RISC architecture, IEE Proceedings, Computers and Digital Techniques 193 (1996) 309-317.
4. A.R. Omondi, Ideas for the design of multithreaded pipelines, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 213-251.
5. D. Grunwald, R. Neves, Whole-program optimization for time and space efficient threads, in: Proc. 7th International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, New York, 1996, pp. 50-59.
6. G.S. Tjaden, M.J. Flynn, Representation and detection of concurrency using ordering matrices, IEEE Transactions on Computers 22 (1973) 752-761.
7. M. Horne, Operand-buffering in pipelined machines, M.Sc. Thesis, Department of Computer Science, Victoria University of Wellington, New Zealand, 1995.
8. P.R. Nuth, W.J. Dally, Named state and efficient context switching, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 201-212.
9. P.R. Nuth, W.J. Dally, The named-state register file: Implementation and performance, in: Proc. 1st IEEE Symposium on High Performance Computer Architecture, IEEE Press, New York, 1995, pp. 4-13.
10. A. Agarwal, Performance tradeoffs in multithreaded processors, IEEE Transactions on Parallel and Distributed Systems 3 (1992) 525-539.
11. R. Thekkath, S.J. Eggers, The effectiveness of multiple hardware contexts, in: Proc. 6th International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, New York, 1994, pp. 328-337.
12. D.E. Culler, Multithreading: fundamental limits, potential gains, and alternatives, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 97-137.
13. H.H.J. Hum, G.R. Gao, Concurrent execution of heterogeneous threads in the super-actor machine, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 317-347.
14. V. Soundararajan, A. Agarwal, Dribble registers: A mechanism for reducing context switch latency in large-scale multiprocessors, Laboratory for Computer Science, Massachusetts Institute of Technology, 1992.
15. D.E. Culler, M. Gunter, J.C. Lee, Analysis of multithreaded microprocessors under multiprogramming, Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994, pp. 351-372.
16. R.A. Iannucci, G.R. Gao, R.H. Halstead, B. Smith, Eds., Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publishers, Boston, 1994.