Validation of numerical models of ceramic pin grid array packages

Microelectronics Journal

Volumn 28, Issue 3, 1997, Pages 229-238

  O'Flaherty, M ^a   Cahill, C ^a   Rodgers, K ^a   Slattery, O ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0040569340     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(96)00027-4     Document Type: Article

References (10)

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8. F. Oettinger, Thermal evaluation of VLSI packages using test chips a critical review, Solid State Technol., 27(2) (Feb. 1984) 169-179.
9. R.L. Kozarek, Effect of case temperature measurement errors on the junction-to-case thermal resistance of a ceramic PGA, 7th SEMITHERM, 1991.
10. J.N. Sweet and W.T. Cooley, Thermal resistance measurements and finite element calculations for ceramic hermetic packages, 6th SEMITHERM, 1990.