Execution-based scheduling for VLIW architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1685 LNCS, Issue , 1999, Pages 1269-1280

  Ebcioǧlu, Kemal ^a   Altman, Erik R ^a   Sathaye, Sumedh ^a   Gschwind, Michael ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Binary translation; Dynamic compilation; Instruction level parallelism; Superscalar

Indexed keywords

ARCHITECTURAL COMPATIBILITY; BINARY TRANSLATION; BRANCH MISPREDICTIONS; DYNAMIC COMPILATION; DYNAMIC SOFTWARES; INSTRUCTION LEVEL PARALLELISM; SCHEDULING TECHNIQUES; SUPERSCALAR;

SCHEDULING;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0039770299     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: None     Document Type: Conference Paper

References (11)

1. K. Ebcioǧlu and E. Altman. DAISY: Dynamic Compilation for 100% Architectural Compatibility. Research Report RC 20538, IBM T.J. Watson Research Center, Yorktown Heights, NY, 1996.
2. K. Ebcioǧlu and E. Altman. DAISY: Dynamic Compilation for 100% Architectural Compatibility. In Proc. of the 24th Annual International Symposium on Computer Architecture, pages 26-37, Denver, CO, June 1997. ACM.
3. K. Ebcioǧlu. Some Design Ideas for a VLIW Architecture for Sequential-Natured Software. In M. Cosnard et al., editor, Parallel Processing, pages 3-21. North-Holland, 1988. (Proceedings of IFIP WG 10.3 Working Conference on Parallel Processing).
4. G. M. Silberman and K. Ebcioǧlu. An Architectural Framework for Migration from CISC to Higher Performance Platforms. In Proc of the 1992 International Conference on Supercomputing, pages 198-215, Washington, DC, July 1992. ACM Press.
5. G. M. Silberman and K. Ebcioǧlu. An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures. IEEE Computer, 26(6):39-56, June 1993.
6. Sun Microsystems. The Java Hotspot Performance Engine Architecture. http://java.sun.com/products/hotspot/whitepaper.html, April 1999.
7. K. Ebcioǧlu, J. Fritts, S. Kosonocky, M. Gschwind, E. Altman, K. Kailas, and T. Bright. An eight-issue tree-VLIW processor for dynamic binary translation. In Proc. of the 1998 International Conference on Computer Design (ICCD '98) - VLSI in Computers and Processors, pages 488-495, Austin, TX, October 1998. IEEE Computer Society.
8. A. Chernoff, M. Herdeg, R. Hookway, C. Reeve, N. Rubin, T. Tye, S. B. Yadavalli, and J. Yates. FX!32-A Profile-Directed Binary Translator. IEEE Micro, 18(2):56-64, March 1998.
9. M. Rosenblum, S. Herrod, E. Witchel, and A. Gupta. Complete Computer Simulation: The SimOS Approach. IEEE Parallel and Distributed Technology, 3(4):34-43, Winter 1995.
10. R. Nair and M. Hopkins. Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups. In Proc of the 24th Annual International Symposium on Computer Architecture, pages 13-25, Denver, CO, June 1997. ACM.
11. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith. Trace Processors. In Proc. of the 30th Annual International Symposium on Microarchitecture, pages 138-148, Research Triangle Park, NC, December 1997. IEEE Computer Society.