Understanding models of substrate behaviour for the routing of high I/O packages

Proceedings - 1998 IEEE Symposium on IC/Package Design Integration, IPDI 1998

Volumn 1998-February, Issue , 1998, Pages 58-63

  Palmer, P J ^a   Williams, D J ^a  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUITS;

FUTURE GENERATIONS; PACKAGED CHIPS; POTENTIAL TECHNOLOGIES;

SUBSTRATES;

EID: 0039750648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDI.1998.663622     Document Type: Conference Paper

References (6)

1. T Chiba, M Yamada and F Kobayashi, Limitation of the Signal Pin Density on Wiring Boards, IEEE CPMT Transactions, 19, 391-396, 1996.
2. K V Guinn and R C Frye, Matching CSP and Flip Chip I/O Density Demands to Printed Wiring Board Capabilities, Chip Scale Review, 16-23, September 1997.
3. T Kimura, Y Yamaji, Y Ohara, Y Matsune, K Miyata, Y Sota, A Narai, K Fujita, and M Kada, CSP Packaging and Mounting Technologies for Mobile Apparatus, 1997 International Symposium on Microelectronics, 256-261.
4. N Chandler and D Wooley, Making the right connection, Future Circuits, 1, No 1, 147-152, 1997
5. D J Williams, P J Palmer and T C Edwards, Technology Trends in Electronics and Photonics, Their Modelling and Effect on Manufacturing and Assembly, Journal of Electronic Manufacturing, 7, 69-77, 1997.
6. H. Mannan. D J Williams and D C Whalley, Some optimum processing properties for anisotropic conductive adhesives for flip chip interconnection, Journal of Materials Science, Materials in Electronics, 8, 223-231, 1997.