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Volumn 45, Issue 12-13, 1999, Pages 939-948

Basic issues in microprocessor architecture

Author keywords

Cache limits; Memory wall; Microprocessor architecture; Program behavior limits; Scaling

Indexed keywords


EID: 0039180032     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(98)00045-9     Document Type: Article
Times cited : (6)

References (13)
  • 2
    • 0027001352 scopus 로고
    • An investigation of the performance of various dynamic scheduling techniques
    • December
    • M. Butler, Y. Patt, An investigation of the performance of various dynamic scheduling techniques, in: Proceedings of MICRO-25, December 1992.
    • (1992) In: Proceedings of MICRO-25
    • Butler, M.1    Patt, Y.2
  • 10
    • 0020177251 scopus 로고
    • Cache memories
    • A.J. Smith, Cache memories, ACM Computing Surveys 14 (3) (1982) 473-530.
    • (1982) ACM Computing Surveys , vol.14 , Issue.3 , pp. 473-530
    • Smith, A.J.1
  • 11
    • 4143052654 scopus 로고
    • Algorithms for Designing High-Performance Digital Circuits Using Wave Pipelining
    • January
    • D. Wong, G. De Micheli, M. Flynn, Algorithms for Designing High-Performance Digital Circuits Using Wave Pipelining, IEEE Transactions on CAD/ICAS, January 1993, pp. 25-46.
    • (1993) IEEE Transactions on CAD/ICAS , pp. 25-46
    • Wong, D.1    De Micheli, G.2    Flynn, M.3
  • 12
    • 0003158656 scopus 로고
    • Hitting the memory wall: Implications and the obvious
    • March
    • W. Wulf, S. McKee, Hitting the memory wall: Implications and the obvious, ACM Computer Architecture News, 13 (1), March 1995.
    • (1995) ACM Computer Architecture News , vol.13 , Issue.1
    • Wulf, W.1    McKee, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.