Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Wang, Xiaoyan ^a   Andreani, Pietro ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; TUNING; VARIABLE FREQUENCY OSCILLATORS;

PHASE-ERROR PERFORMANCE;

INDUCTANCE;

EID: 0038827212     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. P. Andreani. "A Low-Phase-Noise, Low-Phase-Error 1.8GHz Quadrature CMOS VCO" Proc. ISSCC, pp. 290-291, February 2002.
3. 0 Phase Error". Proc. ESSIRC, pp. 815-818, September 2002.
4. X. Wang and P. Andreani. "A 2GHz Low-Phase-Noise CMOS Quadrature VCO". To be presented at NORCHIP, November 2002.
5. S. L. J. Gierkink, S. Levantino, R. C. Frye and V. Boccuzzi. "A Low-Phase-Noise 5GHz Quadrature CMOS VCO using Common-mode Inductive Coupling". Proc. ESSIRC, pp. 539-542, September 2002.
6. P. Andreani, A. Bonfanti, L. Romano, and C. Samori. "Analysis and Design of a 1.8GHz CMOS LC Quadrature VCO". JSSC, December 2002 (to be published).
7. H. M. Greenhouse. "Design of Planar Rectangular Microelectronic Inductors". IEEE Transactions on Parts, Hybrids, and Packaging Vol. Php-10, No. 2, pp. 101-109, June 1974.