Phase noise in a back-gate biased low-voltage VCO

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Kazemeini, Mehdi H ^a   Jamal Deen, M ^a   Naseh, Sasan ^a  

^a McMasterUniversity ^*  (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; SPURIOUS SIGNAL NOISE;

PHASE NOISE;

VARIABLE FREQUENCY OSCILLATORS;

EID: 0038827196     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. M. Jamal Deen, Mehdi H. Kazemeini and Sasan Naseh, "Performance Characteristics of an Ultra-Law Power VCO," Proceedings of IEEE ISCAS 2003.
4. Sung-Mo Kang and Yusuf Leblebici. "CMOS Digital Integrated Circuits" WCB/McGraw-Hill, 1999.
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7. Nills Hedenstierna and Kjell O. Jeppson, "Comments on the optimum CMOS Tapered Buffer Problem". IEEE J. Solid -State Circuits, vol. 29, pp. 155-159, 1994.
8. M. Jamal Deen and Ognian Marinov, "Effect of Forward and Reverse Substrate Biasing on Low Frequency Noise in Silicon PMOSFETs", IEEE Transactions on Electron Devices, vol. 49(3), pp. 409-414, 2002.