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Volumn , Issue , 2003, Pages 57-60
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Towards planar processing for InP DHBTs
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SIMULATION;
ELECTRIC CONDUCTIVITY MEASUREMENT;
HEAT LOSSES;
HETEROJUNCTION BIPOLAR TRANSISTORS;
ION IMPLANTATION;
LSI CIRCUITS;
MOLECULAR BEAM EPITAXY;
PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;
PYROMETERS;
RAPID THERMAL ANNEALING;
SEMICONDUCTING INDIUM PHOSPHIDE;
SEMICONDUCTOR DEVICE STRUCTURES;
CAPACITANCE;
HETEROJUNCTIONS;
INDIUM;
INDIUM PHOSPHIDE;
SUBSTRATES;
TEMPERATURE;
THERMAL CONDUCTIVITY;
DOUBLE HETEROJUNCTION BIPOLAR TRANSISTORS;
METALORGANIC MOLECULAR BEAM EPITAXY;
PLANAR PROCESSING;
SOFTWARE PACKAGE TRIM;
X RAY ROCKING CURVE MEASUREMENT;
SEMICONDUCTOR DEVICE MANUFACTURE;
HETEROJUNCTION BIPOLAR TRANSISTORS;
DEVICE INTEGRATION;
DOPING PROFILES;
DOUBLE HETEROJUNCTION BIPOLAR TRANSISTORS;
HIGH-SPEED PERFORMANCE;
INTEGRATION CAPABILITY;
ION IMPLANTATION TECHNOLOGIES;
PERFORMANCE EVALUATION;
PLANAR PROCESSING;
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EID: 0038825256
PISSN: 10928669
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (4)
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References (7)
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