A novel ACS scheme for area-efficient viterbi decoders

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2003, Pages

  Zhu, Y ^a   Benaissa, M ^a  

^a UNIVERSITY OF SHEFFIELD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS; PARALLEL ALGORITHMS; RANDOM ACCESS STORAGE; STATE FEEDBACK;

PIPELINING SCHEMES; VITERBI DECODERS;

DECODING;

EID: 0038760830     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. M. Bóo, F. Argüello, J. D. Bruguera, R. Doallo and E. L. Zapata, "High-Performance VLSI Architecture for the Viterbi Algorithm," IEEE Trans. Commun., vol. 45, pp. 168-176, Feb. 1997.
4. M. Biver, H. Kaeslin and C. Tommasini, "In-place updating of path metrics in Viterbi decoders," IEEE Journal of Solid-State Circuits, vol. 24, no. 4, pp. 1158-1159, Aug. 1989.
5. S.-Y. Kim, H. Kim and I.-C. Park, "Path metric memory management for minimising interconnections in Viterbi decoders," Electronic Letters, vol. 37, no. 14, pp. 925-926, Jul. 2001.
6. I. M. Onyszchuk, "Truncation length for Viterbi decoding," IEEE Trans. Commun., vol. 39, pp.1023-1026, Jul. 1991.
7. "VirtexTM 2,5V Field Programmable Gate Arrays product specification," http://www.xilinx.com.
8. G. C. Clark, Jr. and J. B. Cain, Error-correction coding for digital communications, Plenum press, New York, 1981.