Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 854-857

  He, Yigang ^a   Sun, Yichuang ^b  

^a HUNAN UNIVERSITY   (China)

^b UNIVERSITY OF HERTFORDSHIRE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT ISOLATION; FAULTY ELEMENTS; MOST LIKELY; NETWORK-BASED; NONLINEAR ANALOG CIRCUITS; NONLINEAR CIRCUIT; OPTIMIZATION APPROACH; SIMULATION EXAMPLE;

ANALOG CIRCUITS; NEURAL NETWORKS;

COMPUTER SIMULATION;

EID: 0038748768     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922372     Document Type: Conference Paper

References (6)

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3. J. W. Bandler, W. Kellermann and K. Madsen, "Nonlinear Ll-optimisation algorithm for design, modeling and diagnosis of networks," IEEE Trans. Circuits and Syst., vol. 34, no.2, pp 174-181, 1987.
4. Y. G. He, X. J. Luo, and G. Y. Qiu, "A neural-based nonlinear l, norm optimization algorithm for diagnosis of networks," J. of Electronics, vol. 15, No. 4, pp.365-371, 1998.
5. Y. Sun and Z. X. Lin. "Fault diagnosis of nonlinear circuits," Journal of Dalian Maritime University, vol.12, No.l, pp.73-83, 1986.
6. A. Cichocki and R. Unbchauen, Neural networks for optimization and signal processing, John Wiley, 1993, chapter 5-7.