A Circuit Concept for Reducing Soft Error in Highspeed Memory Cells

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 1, 1988, Pages 201-203

  Tang, Denny D ^a   Chuang, Ching Te ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0038716878     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.279     Document Type: Article

References (8)

1. G. A. Sai-Halasz and D. D. Tang, “Soft error rates in static bipolar RAMs,” in IEDM Tech. Dig., 1983, pp. 344–347.
2. S. Voldman, L. A. Patrick, and D. T. Wong, “Alpha particle effects on bipolar ECL static arrays,” in ISSCC Dig. Tech. Paper, 1985, pp. 262–263.
3. T. H. Ning etal, “Self-aligned bipolar transistors for high performance and low-powerdelay VLSI,” IEEE Trans. Electron Devices, vol. ED-28, pp. 1010–1013, Sept. 1981.
4. H. Goto, T. Takada, R. Abe, Y. Kawabe, K. Oami, and M. Tanaka, “An isolation technology for high performance bipolar memories—IOP II,” in ÏEDM Tech. Dig., 1982, p. 58.
5. Y. Kato, A. Hotta, and T. Isobe, “Semiconductor memory device.” U.S. Patent 4 314 359, Feb. 2, 1982.
6. K. Yamaguchi etal, “A 3.5 ns, 2W, 29mm2 16kb bipolar RAM,” in ISSCC Dig. Tech. Papers, 1986, pp. 214–215.
7. Y. Nakase, K. Anami, and S. Kayano, “A double wordline structure in HCL RAM,” in Dig. VLSI Tech. Symp1986, pp. 75–76.
8. C. T. Chuang, D. D. Tang, G. P. Li, E. Hackbarth, and R. R. Boedeker, “A 1.0-ns 5-kbit ECL RAM,” IEEE J. Solid-state Circuits, vol. SC-21, no. 5, pp. 670–674, Oct. 1986.