Model-to-hardware correlations in the design of a 50Gb/s package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1248-1252

  Shan, Lei ^a   Meghelli, Mounir ^a   Rylyakov, Alexander ^a   Trewhella, Jean ^a   Oprysko, Modest ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEMULTIPLEXING; FOURIER TRANSFORMS; FREQUENCIES; INSERTION LOSSES; WAVEFORM ANALYSIS;

DEMULTIPLEXER; MODEL TO HARDWARE CORRELATIONS; WAVEFORM DEGRADATION;

ELECTRONICS PACKAGING;

EID: 0038688845     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Lin and D.J. Costello, Jr., "Error Control Coding: Fundamentals and applications." Englewood Cliffs, N.J.: Prentice-Hall, 1983
2. P. Cherry and M. Iskander, "FDTD Analysis of High Frequency Electronic Interconnection Effects", IEEE Transactions on Microwave Theory and Techniques, Vol. 43, No. 10, pp. 2445-2451, Oct 1995.
3. L. Shan, M. Meghelli, J. Kim, T. Trewhella, and M. Oprysko, "Simulation and Design Methodology for a 50Gb/s Multiplexer/Demultiplexer Package", to be published in IEEE Transactions on Advanced Packaging, 2002.