A 5-GHz band I/Q clock generator using a self-calibration technique

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 807-810

  Wang, Sung Ho ^a   Gil, Joonho ^a   Kwon, Ickjin ^a   Ahn, Hyung Ki ^a   Shin, Hyungcheol ^a   Kim, Beomsup ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Berkäna Wireless Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK GENERATION; CLOCK GENERATION CIRCUITS; CLOCK SIGNAL PATHS; DELAY-LOCKED LOOPS; DIRECT CONVERSION RECEIVERS; POLY-PHASE FILTERS; SELF-CALIBRATION TECHNIQUES; TEMPERATURE VARIATION;

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; MICROPROCESSOR CHIPS; SPACE OPTICS;

CALIBRATION;

EID: 0038680711     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. H. Samavati, H. Rategh, T. Lee, "A Fully Integrated 5GHz CMOS Wireless-LAN Receiver," ISSCC Digest of Technical Papers, pp.208-209, Feb. 2001.
2. Behzad Razavi, "Architectures and Circuits for RF CMOS Receivers," Proceedings, 1998 Custom Integrated Circuits Conference, pp.393-400, May 1998.
3. C-H. Park, O. Kim, B. Kim, "A 1.8-GHz Self-Calibrated Phase Locked Loop with Precise I/Q Matching," IEEE Journal of Solid State Circuits, Vol. 36, No. 5, May 2001,pp.777-783.