Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 608-609

  Brisbin, Douglas ^a   Strachan, Andy ^a   Chaparala, Prasad ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; ELECTRIC CURRENTS; HOT CARRIERS; OPTIMIZATION; PERFORMANCE; PRODUCT DESIGN;

TRANSISTOR ARRAYS;

MOSFET DEVICES;

EID: 0038648336     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Strachan et. al., BCTM 2002, p. 41
2. C. Kim et. al., IEDM 2001, p. 887
3. K. Nakamura et. al., BCTM 2000, p. 94
4. V. O'Donovan et. al., IRPS 2000, p. 174
5. D. Brisbin et. al.", IRW 2001, p. 44
6. D. Brisbin et. al., IRPS 2002, p. 105