A fine-grain parallel architecture based on barrier synchronization

Proceedings of the International Conference on Parallel Processing

Volumn 1, Issue , 1996, Pages 247-250

  Dietz, H G ^a   Hoare, R ^a   Mattox, T ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ARCHITECTURE; PARALLEL PROGRAMMING; SUPERCOMPUTERS; SYNCHRONIZATION;

AGGREGATE FUNCTION; BARRIER SYNCHRONIZATION; FINE GRAINS; PARALLEL COMMUNICATION; PARALLEL EXECUTIONS; PROTOTYPE IMPLEMENTATIONS; SIDE EFFECT;

PARALLEL ARCHITECTURES;

EID: 0038620887     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.1996.539061     Document Type: Conference Paper

References (7)

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