Connecting the Maximum Number of Nodes in the Grid to the Boundary with Nonintersecting Line Segments

Journal of Algorithms

Volumn 22, Issue 1, 1997, Pages 57-92

  Palios, Leonidas ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0038534855     PISSN: 01966774     EISSN: None     Source Type: Journal    
DOI: 10.1006/jagm.1995.0798     Document Type: Article

References (10)

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4. K. Hwang and F. A. Briggs, "Computer Architecture and Parallel Processing," McGraw-Hill, New York, 1985.
5. S. Y. Kung, S. N. Jean, and C. W. Chang, Fault-tolerant array processors using single-track switches, IEEE Trans. Comput. 38 (1989), 501-514.
6. E. M. McCreight, Priority search trees, SIAM J. Comput. 14 (1985), 257-276.
7. K. Mehlhorn, "Data Structures and Algorithms," Vol. 3, Springer-Verlag, Berlin, 1984.
8. R. Raghavan, J. Cohoon, and S. Sahni, "Manhattan and Rectilinear Wiring," Technical Report 81-5, Computer Science Dept., University of Minnesota, Minneapolis, 1981.
9. V. P. Roychowdhury and J. Bruck, "On finding non-intersecting paths in grids and its application in reconfiguring VLSI/WSI arrays," in Proc. 1st Annual Symposium on Discrete Algorithms, 1990.
10. A. D. Singh, Interstitial redundancy: An area efficient fault tolerance scheme for large area VLSI processor arrays, IEEE Trans. Comput. 37 (1988), 1398-1410.