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Volumn 4, Issue , 2001, Pages 61-64

A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKES; LOW POWER ARCHITECTURE; MEMORY STRUCTURE; SOFT-OUTPUT VITERBI ALGORITHM; TRACEBACK; TURBO DECODING;

EID: 0038411536     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922169     Document Type: Conference Paper
Times cited : (8)

References (9)
  • 3
    • 0024908946 scopus 로고
    • A viterbi algorithm with soft-decision outputs and its applications
    • J. Hagenauer. P. Hoeher. "A Viterbi Algorithm with soft-decision outputs and its applications." Proceedings of IEEE Globeeom Conference, 1989, pp. 1680-1686.
    • (1989) Proceedings of IEEE Globeeom Conference , pp. 1680-1686
    • Hagenauer, J.1    Hoeher, P.2
  • 4
    • 0027297430 scopus 로고    scopus 로고
    • A low complexity soft-output viterbi decoder architecture
    • C. Berrou. et. al., "A Low Complexity Soft-Output Viterbi Decoder Architecture," Proceedings of 1993 ICC, p. 737.
    • Proceedings of 1993 ICC , pp. 737
    • Berrou. Et. Al, C.1
  • 5
    • 0026823944 scopus 로고
    • A VLSI design for a trace-back viterbi decoder
    • March
    • T. Trung, et. al. "A VLSI Design for a Trace-Back Viterbi Decoder," IEEE Trans, on Communications. Vol. 40, No. 3. March 1992. p. 616-624.
    • (1992) IEEE Trans, on Communications , vol.40 , Issue.3 , pp. 616-624
    • Trung, T.1
  • 6
    • 0023995238 scopus 로고
    • Locally connected vlsi architectures for viterbi algorithm
    • April
    • P. Gulak. T. Kailath, "Locally Connected VLSI Architectures for Viterbi Algorithm," IEEE Journal on Selected Areas in Communications. Vol. 6, No. 3, April 1988, p. 527-537.
    • (1988) IEEE Journal on Selected Areas in Communications , vol.6 , Issue.3 , pp. 527-537
    • Gulak, P.1    Kailath, T.2
  • 7
    • 0027641448 scopus 로고
    • Novel viterbi decoder vlsi implementation and its performance
    • August
    • S. Kubota, S. Kato, "Novel Viterbi Decoder VLSI Implementation and its Performance," IEEE Transactions on Communications. Vol. 41. No. 8, August 1993, p. 1170.
    • (1993) IEEE Transactions on Communications , vol.41 , Issue.8 , pp. 1170
    • Kubota, S.1    Kato, S.2
  • 8
    • 0039580582 scopus 로고    scopus 로고
    • Master of Science Thesis. University of California Berkeley
    • T. Burd. Low-Power CMOS Libraiy Methodology. Master of Science Thesis. University of California Berkeley.
    • Low-Power CMOS Libraiy Methodology
    • Burd, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.