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Volumn 4, Issue , 2001, Pages 61-64
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A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications
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Author keywords
[No Author keywords available]
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Indexed keywords
BUILDING BLOCKES;
LOW POWER ARCHITECTURE;
MEMORY STRUCTURE;
SOFT-OUTPUT VITERBI ALGORITHM;
TRACEBACK;
TURBO DECODING;
PIPELINES;
TURBO CODES;
DECODING;
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EID: 0038411536
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2001.922169 Document Type: Conference Paper |
Times cited : (8)
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References (9)
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