A JPEG chip for image compression and decompression

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 35, Issue 1, 2003, Pages 43-60

  Sun, Sung Hsien ^a   Lee, Shie Jue ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

CAD tools; FPGA; Image compression decompression; Standard cell design; VHDL; VLSI chip

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; VLSI CIRCUITS;

IMAGE DECOMPRESSION; JOINT PHOTOGRAPHIC EXPERTS GROUP; STANDARD CELL DESIGN;

IMAGE CODING;

EID: 0038353871     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1023383820503     Document Type: Article

References (16)

1. "JPEG digital compression and coding of continuous-tone still image," Technical Report Draft ISO 1991. 1991.
2. "Coding of moving pictures and associated audio," Committee Draft of Standard ISO11172: ISO/MPEG/90/176, 1990.
3. "Video codec for audio visual services at p × 64 k bits per second," CCITT Recommendation H.261, 1990. 1990.
4. K. Sayood, Introduction to Data Compression. San Francisco, CA: Morgan Kaufmann, 2000.
5. P.A. Ruetz, P. Tong, D. Luthi, and P.H. Ang, "A Video-Rate JPEG Chip Set," Journal of VLSI Signal Processing, vol. 5, 1993, pp. 29-38.
6. H. Park and V.K. Prasanna, "Area efficient VLSI architectures for Huffman coding," IEEE Transactions on Circuits and Systems, 1993, pp. 568-575.
7. A. Mukherjee, N. Ranganathan, J.W. Flieder, and T. Acharya, "MARVLE: A VLSI Chip for Data Compression Using Tree-Based Codes," IEEE Transactions on Very Large Scale Integration Systems, 1993, pp. 203-213.
8. Y.S. Lee, J.J. Jong, T.S. Perng, L.C. Hsu, M.Y. Jaw, and C.Y. Lee, "A Memory-Based Architecture for Very-High-Throughput Variable Length Codec Design," IEEE International Symposium on Circuits and Systems, June 1997, pp. 2096-2099.
9. M. Sun, T. Chen, and A.M. Gottlieb, "VLSI Implementation of a 16 × 16 Discrete Cosine Transform," IEEE Transactions on Circuits and Systems, 36, 1989, pp. 610-617.
10. S.-F. Hsiao and J.-M. Tseng, "Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Coding," Journal of VLSI Signal Processing, vol. 28, no. 3, 2001, pp. 205-220.
11. S.A. White, "Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review," IEEE ASSP Magazine, June 1989, pp. 4-17.
12. I. Koren, Computer Arithmetic Algorithm, Prentice-Hall International Editions, 1993.
13. M. Kovac and N. Ranganathan, "JAGUAR: A Fully Pipelined VLSI Architecture for JPEG Image Compression Standard," Proceedings of the IEEE, vol. 83, no. 2, 1995, pp. 247-258.
14. S. Okada, Y. Matsuda, T. Watanabe, and K. Kondo, "A Single Chip Motion JPEG Codes LSI," IEEE Transactions on Consumer Electronics, vol. 43, no. 3, 1997, pp. 418-422.
15. S.K. Asada, H. Ohtsubo, T. Fujihara, and T. Imaide, "Development of a Low-Power MPEG1/JPEG Encode/Decode IC," IEEE Transactions on Consumer Electronics, vol. 43, no. 3, 1997, pp. 639-644.
16. J.K. Hunter, J.V. McCanny, A. Simpson, Y. Hu, and J.G. Doherty, "JPEG Encoder System-on-a-Chip Demonstrator," in Proceedings of the Thirty-Third Asilomar Conference, vol. 1, 1999, pp. 762-766.