A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 53-55+477

  Chen, Feng ^a   Ramaswamy, Srinath ^a   Bakkaloglu, Bertan ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITORS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPARATOR CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; LOW PASS FILTERS; MATHEMATICAL MODELS; MODULATORS; SIGNAL FILTERING AND PREDICTION; SIGNAL INTERFERENCE; TRANSCEIVERS;

ANTI-ALIASING FILTERING; CHANNEL SELECTION FILTER; DIGITAL COMMUNICATION RECEIVER; PASSIVE SWITCHED CAPACITOR; SIGMA DELTA MODULATOR;

CMOS INTEGRATED CIRCUITS;

EID: 0038306658     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A. Namdar and B.Leung "A 400MHz, 12-bit 18 mW IF Digitizer with Mixer Inside a Sigma-Delta Modulator Loop," ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 1999.
2. S. Sen and B. Leung, "A 150MHz 13-bit 12.5 mW IF Digitizer," Proceedings of CICC, pp. 233-236, May, 1998.
3. H. Tenhunen et al., "A Fifth-order Comb Decimation Filter for Multistandard Transceiver Applications," Proc. of ISCAS 2000, pp. II 89-92.