A 2GHz 16dBm IIP3 low noise amplifier in 0.25μm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Youn, Yong Sik ^a   Chang, Jae Hong ^a,b   Koh, Kwang Jin ^a   Lee, Young Jae ^c   Yu, Hyun Kyu ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); FIELD EFFECT TRANSISTORS; GAIN MEASUREMENT; HARMONIC ANALYSIS; INTERMODULATION; SEMICONDUCTOR DEVICE STRUCTURES; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE; TRIODES;

DELAY EQUALIZATION; FRIIS EQUATION; LOW NOISE AMPLIFIER; NOISE FIGURE; THIRD ORDER INTERMODULATION; THIRD-HARMONIC CANCELLATION TECHNIQUE;

CMOS INTEGRATED CIRCUITS;

EID: 0038306219     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Yongwang Ding et al., "A +18dBm IIP3 LNA in 0.35μm CMOS," IEEE ISSCC Digest of Technical Papers, pp. 162-163, 2001.
2. S. Tanaka et al., "A Linearization Technique for CMOS RF Power Amplifiers," IEEE VLSI Circuits Digest of Technical Papers, pp. 93-94, 1997.
3. Min-Gun Kim et al., "An FET-Level Linearization Method using a Predistortion Branch FET," IEEE Microwave Guided Wave Letters, pp. 233-235, 1999.
4. Yong-Sik Youn et al., "A 2GHz RF Front-End Transceiver Chipset in CMOS Technology for PCS and IMT-2000 Applications," IEEE RFIC Digest of Papers, pp. 271-274, 2002.
5. A. A. Abidi et al., "De-Embedding the Noise Figure of Differential Amplifiers," IEEE J. Solid-State Circuits, pp. 882-885, 1999.