A placement algorithm for FPGA designs with multiple I/O standards

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1896, Issue , 2000, Pages 211-220

  Anderson, Jason ^a   Saunders, Jim ^a   Nag, Sudip ^a   Madabhushi, Chari ^a   Jayaraman, Rajeev ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; RECONFIGURABLE ARCHITECTURES; SIMULATED ANNEALING;

DELETERIOUS EFFECTS; FPGA DESIGN; PLACEMENT ALGORITHM; PLACEMENT PROBLEMS; REFERENCE VOLTAGES; STATE OF THE ART; WEIGHTED BIPARTITE MATCHINGS; WIRE LENGTH;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 0038256695     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44614-1_24     Document Type: Conference Paper

References (7)

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