Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 606-607

  Ershov, M ^a   Lindley, R ^a   Saxena, S ^a   Shibkov, A ^a   Minehane, S ^a   Babcock, J ^a   Winters, S ^a   Karbasi, H ^a   Yamashita, T ^a   Clifton, P ^a   Redford, M ^a  

^a PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; EXTRAPOLATION; STRESSES;

NEGATIVE BIAS THERMAL INSTABILITY (NBTI);

MOSFET DEVICES;

EID: 0037972043     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. EE Times, April 12, 2002, "Reliability scales up as CMOS scales down".