Analog weight buffering strategy for CNN chips

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2003, Pages

  Linan Cembrano G ^a   Rodriguez Vazquez A ^a   Carmona, R ^a   Espejo, S ^a   Dominguez Castro R ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; SIGNAL PROCESSING;

BUFFERING STRATEGIES;

CELLULAR NEURAL NETWORKS;

EID: 0037744874     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez, "ACE4k: An Analog I/O 64 × 64 Visual Microprocessor Chip with 7-bit Analog Accuracy". International Journal of Circuit Theory and Applications, Vol. 30, pp. 89-116, March-June 2002.
2. G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez, "Architectural and Basic Circuit Considerations for a Flexible 128 × 128 Mixed-Signal SIMD Vision Chip". Analog Integrated Circuits and Signal Processing, Vol.33, No. 2, pp. 179-190, November 2002.
3. R. Carmona, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo, T. Roska, C. Reckezki and A. Rodríguez-Vázquez, "A Bio-Inspired 2-Layer Mixed-Signal Mixed-Signal Flexible Programmable Chip for Early Vision". IEEE Transactions on Neural Networks, (submitted).
4. A. Rodríguez-Vázquez, G. Liñán, S. Espejo and R. Domínguez-Castro, "Mismatch-Induced Trade-offs and Scalability of Analog Preprocessing Visual Microprocessor". Analog Integrated Circuits and Signal Processing, to appear in 2003.